1. Field of the Invention
The invention relates to Dynamic Random Access Memories (DRAMS), and more particularly to improvement in the process of preparing DRAMS to overcome the small opening of a DRAM trench due to the small ground rules in the formation of an isolation collar on trench sidewalls, by utilizing a process flow which uses a thin dielectric replacement collar for all DT processes until the DT fill, and after a recess, forming the final collar in a second step.
2. Description of the Prior Art
Deep trench (DT) based storage devices are used in DRAM cells, and these devices are generally etched from about 4 to 8 microns deep into the silicon substrate. Further, while the process for forming the deep trench differs between 4 Mb up to 1GB DRAM cells, nevertheless, there are a certain number of process steps common to each of the five generations of DRAM cells.
The commonly used deep trench processing steps, which form a large portion of the cost of making each of these trench-based DRAM cells are:
etching of a deep trench;
deposition of a node dielectric by low pressure chemical vapor deposition (LPCVD) of SiN;
reoxidation of the node dielectric;
deposition of a first polysilicon fill using LPCVD;
chemical mechanical polish of the first polysilicon fill;
etching of a first recess in the first polysilicon fill using reactive ion etching (RIE);
deposition of a collar oxide;
etching of the collar oxide at the bottom using RIE;
deposition of a second polysilicon fill using LPCVD; and
chemical mechanical polish of the second polysilicon fill.
A connection between the storage trench and its associated array transistor is provided by a third polysilicon recess that is generally etched about 50 nm below the silicon surface. This processing step is generally referred to as the xe2x80x9cburied strap formationxe2x80x9d. The process step of forming the buried strap formation complicates the deep trench process.
A method of fabricating a storage node for a deep trench-based DRAM on a semiconductive substrate is disclosed in U.S. Pat. No. 5,656,535. The method entails:
etching a trench in a surface of the substrate;
forming a layer of dielectric material on a sidewall of the trench;
partially removing the layer of dielectric material to expose an underlying region of an upper portion of the sidewall;
growing a layer of oxide on the upper portion of the sidewall;
removing a portion of the layer of oxide from the sidewall to orient the layer of oxide a predetermined distance from the surface of the substrate; and
filling the trench with a semiconductive material.
U.S. Pat. No. 5,395,786 disclose a method for forming a DRAM cell in a semiconductor substrate of a first polarity comprising:
forming a temporary protective layer on the surface of the substrate;
etching a trench vertically to a first depth, exposing upper trench sidewalls and a first trench bottom;
expanding the trench horizontally by substantially isotropic etching of the upper trench sidewalls under the temporary protective layer to form trench collar sidewalls displaced from the upper trench sidewalls by a sidewall offset distance;
forming a layer of collar dielectric having a thickness substantially equal to the sidewall offset distance on the collar sidewalls and on the first trench bottom;
removing the collar dielectric from at least the first trench bottom;
etching the trench further through the first trench bottom to a final trench depth having a final trench bottom and lower trench sidewalls;
doping the lower trench sidewalls with a sidewall dose of the second polarity;
forming a trench dielectric on at least the lower trench sidewalls;
forming an inner electrode within the trench etching the inner electrode and the collar dielectric to a strap depth, thereby exposing a strap contact surface on a portion of the collar sidewalls and an electrode contact surface on the top of the inner electrode;
forming a conductive strap between the strap contact surface and the inner electrode; and
forming an access transistor having a strap contact electrode abutting the strap contact surface.
The conventional methods known in the art for forming a collar in the upper part of the DRAM trench suffer from the following drawbacks:
If the collar formation is done after the formation of the storage capacitor in the bottom part of the trench, it is not possible to use techniques like trench bottle process or self aligned formation of a buried plate. Both these techniques require the collar to be in place at the beginning of the trench processing.
Alternatively, if the collar formation is done before the formation of the storage capacitor in the bottom part of the trench, bottle formation and self aligned buried plate formation are possible. However, the small trench opening is significantly reduced by the formation of the isolation collar on the trench sidewalls. It is therefore extremely difficult to execute all DT process steps after collar formation. In addition, the thickness of the polysilicon layer in the trench acting as inner electrode of the storage capacitor is extremely thin.
Accordingly, there is a need in the art of preparing a trench DRAM processing scheme to devise a means to provide as complete a full trench opening as possible during trench processingxe2x80x94and this is especially important when node dielectric with high dielectric constants are used.
One object of the present invention is to provide a process for eliminating the very small opening of a DRAM trench in the usual trench DRAM processing for small ground rules.
Another object of the present invention is to provide a process for eliminating the very small opening of a DRAM trench in the usual trench DRAM processing for small ground rules, in which the small opening has been further reduced by the formation of an isolation collar on the trench sidewalls.
A further object of the present invention is to provide a process for eliminating the very small opening of a DRAM trench in usual trench DRAM processing for small ground rules, in which the small opening has been further reduced by the formation of an isolation collar on the trench sidewalls, wherein it is extremely difficult to execute all DT process steps after collar formation until the DT fill.
The foregoing and other objects of the present invention will become apparent by reference to the drawings and detailed description of the preferred embodiment hereinafter set forth.